Clock regeneration circuit and optical signal receiver using the same

ABSTRACT

Disclosed is a clock regeneration circuit comprising a PLL circuit which includes a voltage control oscillator, for synchronizing an oscillation frequency signal of the voltage control oscillator with a phase of a reception signal; a clock extraction circuit which includes a band passing filter having a passing band width which concurrently extracts a basic waves component of the oscillation frequency signal of the voltage control oscillator and a harmonic component of a dividing signal of the oscillation frequency signal, for extracting a clock component of the reception signal; a frequency detector for detecting a different in frequencies between an output of the clock extraction circuit and an oscillation frequency of the voltage control oscillator; a filter for controlling the oscillation frequency of the voltage control oscillator of the PLL circuit at a detection output of the frequency detector; a bit rate detection circuit for detecting a bit rate of the reception signal; and a frequency selection circuit for outputting an oscillation frequency of the voltage control oscillator of the PLL circuit or a frequency signal obtained by dividing the oscillation frequency in response to the bit rate detected by the bit rate detection circuit, as a regeneration clock signal.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a clock regeneration circuit,and in particular to a bit free clock regeneration circuit which enablesa clock extraction not depending on a bit frequency, and an opticalsignal receiver using the same.

[0003] 2. Description of the Related Arts

[0004] In a transmitter, a clock of a reception signal is extracted as aself-synchronous type, and a reception timing of the reception signal isdetermined in synchronism therewith. For this reason, a clockregeneration circuit for extracting the clock from the reception signalis necessary.

[0005] Until now, in a transmission system, generally speaking, a bitrate of the clock in the reception signal is already known, and theclock regeneration circuit at a receiver side was structuredcorresponding to this fact. A SAW filter is used, or a PLL system isused, and a circuit for extracting and regenerating the clocks of adevotedly signal frequency is used as a clock regeneration circuit.

[0006] On the other hand, in recent years, an optical transmissionsystem is spread, and the transmission of a large capacity is furtherpossible due to an optical multiplexing.

[0007]FIG. 1 is an example of an optical transmission system, and in aconfiguration of a transmission side device 20, a multiplexer 200multiplexes a signal, and an optical transmitter 201 converts it into anoptical signal of a single wavelength to transmit it to a reception sidedevice 21 via an optical fiber transmission path 22.

[0008] In the reception side device 21, a light receiving element 210converts the received lights into an electric signal, and apre-amplifier 211 and a main amplifier 212 amplify it to a predeterminedlevel. Furthermore, the amplified reception signal are sent to adiscriminator 214 and a clock regeneration circuit 213.

[0009] The clock regeneration circuit 213 extracts a clock signalsynchronized with a frequency of the reception signal. At a timing of aclock signal extracted, the discriminator 214 discriminates and outputsthe reception signal as data. Furthermore, the clock signal is sent to amultiplexing separation circuit 215 to separate the multiplexing of thereception signal discriminated and output from the discriminator 214.

[0010] Here, the optical transmission system in FIG. 1 uses an opticaltransmission signal of clock frequencies of 155 Mb/s, 622 Mb/s, or 2.4Gb/s in response to the transmission capacity. Accordingly, it isnecessary that the clock regeneration circuit 213 of the opticalreception side device 21 prepares the clock regeneration circuits 213differing respectively corresponding to the clock frequencies for use inthe transmission system.

[0011] Furthermore, in recent years, in an optical communication,development and practical use of a wavelength division multiplexingcommunication system are being advanced. The wavelength divisionmultiplexing communication system transmits an optical signal of a largecapacity in which frequencies are divided and multiplexed by a WDM(Wavelength Division Multiplexing) system. FIG. 2 is a configurationalexample of such the wavelength division multiplexing system. An existentsystem 30 as a transmission side device is a signal source forgenerating and outputting a plurality of optical signals.

[0012] A separate optical signal from the existent system 30 isreceived, and an optical/electric signal converter 31 converts it into acorresponding electric signal. The optical/electric signal converter 31converts into an electric signal, and after a predetermined signalprocessing is effected, an electric/optical signal converter 32 againconverts it into an optical signal.

[0013] The plurality of optical signals from the electric/optical signalconverter 32 are converted into an optical signal of a wavelengthcorresponding to each signal by an optical multiplexer 33, whichtransmits it to an optical transmission path 34 as a wavelength divisionmultiplexing signal.

[0014] A wavelength division multiple optical signal propagates throughthe optical transmission path 34, and is input to an opticalmultiplexing separator 35 of the reception side device. The wavelengthdivision multiplexing optical signal is separated to a separate opticalsignal in each wavelength, and is converted into an electric signal by acorresponding optical/electric signal converter 36.

[0015] As occasion demands, an electric/optical signal converter 37again converts into an optical signal, and an existent system 38converts it into an electric signal, and a separate optical signal isprocessed in each wavelength.

[0016] Accordingly, in a system example of FIG. 2, in the existentsystem, the clock regeneration circuit corresponding to each wavelengthis necessary.

SUMMARY OF THE INVENTION

[0017] In light of problems in the conventional system, it is an objectof the present invention to extract a clock in a common circuit with aplurality of clock signals.

[0018] it is another object of the present invention to provide a bitfree clock regeneration circuit capable of extracting clocks ofdifferent bit rates of the wavelength division multiplexing opticalreception signal with a type of circuit configuration when being used asan optical receiver, and an optical signal receiver using the same.

[0019] As for a basic concept in the clock regeneration circuit whichsolves problems in the present invention, the clock regeneration circuitcomprises a clock extraction circuit having a band pass filter having awide range of passing frequencies, and an oscillation frequency of avoltage control oscillation in a PLL circuit agrees with basic waves orharmonic waves of a signal. Thereafter, a phase with the signal iscontrolled at a discrimination optimal point. Next, the bit rate of dataof an output signal is detected, and the clock in synchronism with thesignal is regenerated. Thereby, the bit free clock regenerator and theoptical signal receiver using the same are realized.

[0020] In order to solve the above problems, according to an aspect ofthe present invention there is provided a clock regeneration circuit,comprising a PLL circuit which comprises a voltage control oscillator,and synchronizes an oscillation frequency signal of the voltage controloscillator with a phase of a reception signal; a clock extractioncircuit which comprises a band passing filter having a passing bandwidth which concurrently extracts a basic waves component of theoscillation frequency signal of the voltage control oscillator and aharmonic component of a dividing signal of the oscillation frequencysignal, and extracts a clock component of the reception signal; afrequency detector for detecting a different in frequencies between anoutput of the clock extraction circuit and an oscillation frequency ofthe voltage control oscillator; a filter for controlling the oscillationfrequency of the voltage control oscillator of the PLL circuit at adetection output of the frequency detector; a bit rate detection circuitfor detecting a bit rate of the reception signal; and a frequencyselection circuit for outputting an oscillation frequency of the voltagecontrol oscillator of the PLL circuit or a frequency signal obtained bydividing the oscillation frequency in response to the bit rate detectedby the bit rate detection circuit, as a regeneration clock signal.

[0021] Preferably, the clock extraction circuit further comprises adelay circuit for delaying the reception signal by the half cycle; andan EX-OR circuit for acquiring an exclusive OR operation of an output ofthe delay circuit and the reception signal, wherein the output of theEX-OR circuit is led to the band passing filter in the configuration.

[0022] Preferably, the bit rate detection circuit comprises a first ANDgate for taking a conjunction of the reception signal and theoscillation frequency signal of the voltage control oscillator of thePLL circuit; a delay circuit for delaying an output of the first ANDgate by 1 cycle of the oscillation frequency signal of the voltagecontrol oscillator; a second AND gate for taking a conjunction of anoutput of the first AND gate and an output of the delay circuit; and acircuit for acquiring an average value of the output of the AND gate.

[0023] Preferably, the bit rate detection circuit comprises an AND gatefor synthesizing the reception signal with a signal obtained byinverting the reception signal; and a circuit for acquiring an averagevalue of the output of the AND gate.

[0024] Preferably, the bit rate detection circuit comprises an AND gatefor synthesizing the reception signal with a signal obtained byinverting the reception signal; and a circuit for counting a changepoint of the output of the AND gate.

[0025] The above and other objects, aspects, features and advantages ofthe present invention will become more apparent from the followingdescription of the preferred embodiments when read in conjunction withthe accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 is a block diagram of a configurational example showing oneexample of an optical transmission system;

[0027]FIG. 2 is a block diagram with a configurational example of awavelength division multiplexing system;

[0028]FIG. 3 is a diagram showing an embodiment configuration of a clockextraction circuit according to the present invention, applied to anoptical receiver;

[0029]FIG. 4 is a diagram for explaining a band width of a band passfilter 1 and a control range of a voltage control oscillator 7.

[0030]FIG. 5 is a detailed circuit example in the block diagram of theembodiment of FIG. 3;

[0031]FIG. 6 is a block diagram showing a configuration of a main partof a clock extraction circuit 15;

[0032]FIG. 7 is an operational waveform diagram in each part of FIG. 6;

[0033]FIG. 8 is a diagram showing a passing band of a band pass filter13 of FIGS. 5 and 6;

[0034]FIG. 9 is a block diagram showing a configuration of a main partof a bit rate detection circuit 10;

[0035]FIG. 10 is a waveform view in response to respective parts {circleover (1)} to {circle over (3)} of FIG. 9;

[0036]FIG. 11 is a second detailed circuit example in the lock diagramof the embodiment of FIG. 3; and

[0037]FIG. 12 is a diagram for explaining the case where a bit rate isdetected utilizing an edge of data in the configuration of FIG. 11.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0038] An embodiment of the present invention will now be described withreference to the drawings. Incidentally, the same reference numerals orreference symbols are assigned to the same or similar components in thedrawings for explanation.

[0039]FIG. 3 is a diagram showing a configuration of a clockregeneration circuit according to the embodiment of the presentinvention which is applicable to an optical receiver. In FIG. 3, areceived optical signal is converted into an electric signal by a lightreception element 1. The received optical signal which is converted intothe electric signal is amplified up to a discriminable level through apre-amplifier 2 and a main amplifier 3.

[0040] An output of the main amplifier 3 is input to a clock extractioncircuit 15 and a PLL circuit 4 configuring the clock regenerationcircuit having characteristics according to the present invention.

[0041] In a clock component generation circuit 12 of the clockextraction circuit 15, a clock component is output from the inputreception signal. Next, in a band pass filter 13 as a clock extractionfunction part having a wide band width, the clock frequency component isextracted.

[0042] An output of the band pass filter 13 is amplified by an AGCamplifier 14 and is input to a frequency detector 16.

[0043] The frequency detector 16 compares a clock frequency from the AGCamplifier 14 with an output frequency of a voltage control oscillator 7of the PLL circuit 4 which is input through a selection circuit 8.

[0044] At a point of time when agreed in frequency comparison, an outputdirection of the selector 8 is switched, and a phase detector 5phase-compares a reception signal from a main amplifier 3 with an outputof the voltage control oscillator 7.

[0045] Here, a band width of the band pass filter 3 agrees with acontrol range of the voltage control oscillator 7 as in FIG. 4. Namely,FIG. 4A is a passing band characteristic of the band pass filter 13,having a passing band width 1.35 GHz to 2.7 GHz as the embodiment. Onthe other hand, FIG. 4B is a diagram showing a control voltage versusoscillation frequency characteristic of the voltage control oscillator7.

[0046] As shown in FIG. 4B, the voltage control oscillator 7 outputs afrequency signal of 1.35 GHz to 2.7 GHz so as to correspond to thepassing band width of the band pass filter 13 in the range of thecontrol voltages V1 to V2. By such the setting, a capture range iswidened.

[0047] For example, as shown in FIG. 4, in the case where the frequencyranges of the band pass filter 13 and voltage control oscillator 7 areset to be 1.35 GHz to 2.7 GHz, and an input signal is set as 155 Mb/s,the clock components of 2.4 GHz as harmonic components of the inputsignal of 155 Mb/s are output from the band pass filter 13.

[0048] Until these clock components agree with the output frequencies ofthe voltage control oscillator 7 by the frequency detector 16, thevoltage control oscillator 7 is controlled in a voltage through a loopfilter 6.

[0049] In this manner, in the present invention, it is possible toreceive a bit rate of 1 over an integer in the range of the frequencies,and to realize a bit rate free.

[0050] Next, the oscillation frequency of the voltage control oscillator7 is input to a discriminator 9, and also is input to a bit ratedetector 10. The discriminator 9 detects a level of a reception signalat an oscillation frequency timing of the voltage control oscillator 7,and outputs it as reception data.

[0051] Incidentally, 155 Mb/s was available as the above embodiment, butthe present invention is not limited thereto. Namely, the presentinvention is applicable to 155 Mb/s, 600 Mb/s, and 2.4 Gb/s as theexistent bit rates, and additionally is applicable to a bit rate otherthan these existent bit rates, for example 125 Mb/s, too.

[0052] A bit rate detector 10 inputs output data of the discriminator 9,and detects the bit rate of these data at an oscillation frequencytiming of the voltage control oscillator 7. A clock selection circuit 11selects a clock agreeing with the bit rate to output it.

[0053] Incidentally, as a method for detecting the bit rate in the bitrate detector 10, as explained in detail below, there are a method forconverting the data into a RZ signal and a method for detecting an edgeof the data.

[0054]FIG. 5 is an example of a detailed circuit in the block diagramaccording to the embodiment of FIG. 3.

[0055] A discrimination circuit 9 is constituted by a flip-flop, and aclock component generation circuit of the clock extraction circuit 15 isconfigured by a delay circuit 120 and an exclusive OR operation (EX-OR)circuit 121, as shown in FIG. 6. An output of the exclusive OR operation(EX-OR) circuit 121 is input to the band pass filter 13.

[0056] This clock extraction circuit 15 utilizes f₀ components of theinput signal, and in the circuit shown in FIG. 6, in the case where theinput signals are an alternative of “1” and “0”, for clarity of thedescription, output waveforms in each part in FIG. 6 are shown in{circle over (1)} to {circle over (3)} of FIG. 7.

[0057] Assume that the input waveforms are basically rectangular waves,the output {circle over (3)} of the exclusive OR operation (EX-OR)circuit 121 becomes a cyclic pulse as shown in formula 1.$\begin{matrix}{{v(t)} = {\frac{t_{0}}{T}{\sum\limits_{n = 1}^{\infty}\quad {\frac{2}{n\quad \pi}\sin \frac{n\quad \pi}{T}{t \cdot \cos}\quad n\quad \omega \quad t}}}} & 1\end{matrix}$

[0058] Accordingly, respective frequency spectra of the basic waves f₀and 1 over an integer of the basic waves f₀ are as follows:

f=f₀

v1(t)=a₀+a₁ cos 2πf₀+a₂ cos 4πf₀+a₃ cos 6πf₀+ . . . +a_(n) cos 2nπ f₀

[0059]${a_{0} = {\frac{t_{0}}{T_{0}} = {1/2}}},\quad {a_{n} = {{\frac{2}{n\quad \pi}\sin \frac{n\quad \pi}{T_{0}}t_{0}} = {\frac{2}{n\quad \pi}\sin \frac{n\quad \pi}{2}}}}$

 f=f₀/2

v2(t)=a₀+a₁ cos 2πf₀/2+a₂ cos 4πf₀/2+a₃ cos 6πf₀/2+ . . . +a_(n) cos2nπf₀/2

[0060]  =a₀+a₁ cos πf₀+a₂ cos 2πf₀+a₃ cos 3πf₀+ . . . +a_(n) cos nπf₀${a_{0} = {\frac{t_{0}}{T_{0}} = {1/4}}},\quad {a_{n} = {{\frac{2}{n\quad \pi}\sin \frac{n\quad \pi}{T_{0}}t_{0}} = {\frac{2}{n\quad \pi}\sin \frac{n\quad \pi}{4}}}}$

 f=f₀/3

v3(t)=a₀+a₁ cos ⅔πf₀+a₂ cos {fraction (4/3)}πf₀+a₃ cos 2πf₀+ . . . +a_(n) cos n/3πf₀

[0061]${a_{0} = {\frac{t_{0}}{T_{0}} = {1/6}}},\quad {a_{n} = {{\frac{2}{n\quad \pi}\sin \frac{n\quad \pi}{T_{0}}t_{0}} = {\frac{2}{n\quad \pi}\sin \frac{n\quad \pi}{6}}}}$

 f=f₀/4

v4(t)=a₀+a₁ cos ½πf₀+a₂ cos πf₀+a₃ cos {fraction (3/2)}πf₀+a₄ cos 2πf₀+. . . +a_(n) cos n/4πf₀

[0062]${a_{0} = {\frac{t_{0}}{T_{0}} = {1/8}}},\quad {a_{n} = {{\frac{2}{n\quad \pi}\sin \frac{n\quad \pi}{T_{0}}t_{0}} = {\frac{2}{n\quad \pi}\sin \frac{n\quad \pi}{8}}}}$

[0063] Here, when a passing band BPF of the band pass filter 13 of FIGS.5 and 6 has a wide band width as shown in FIG. 8, both in the case off=f₀ and in the case of f=f₀/n, only a term of 2πf₀ of the above formulais selected to be output as a clock f₀.

[0064] That is, in the case of f=f₀, basic waves (the second term), andin the case of f=f₀/2, secondary harmonic waves (the third term), and inthe case of f=f₀/3, tertiary harmonic waves (the fourth term), and inthe case of f=f₀/4, quartic harmonic waves (the fifth term), spectrumcomponents thereof agree with each other within the passing band widthBPF of the band pass filter 13 to be output.

[0065] Thus, even at any bit rate speed, harmonic components of thefrequencies set by the band pass filter 13 exist.

[0066] The AGC amplifier 14 amplifies an amplitude of these harmoniccomponents up to a constant amplitude, and as described previously, itis compared with the oscillation frequency of the voltage controloscillator 7.

[0067] Furthermore, in FIG. 5, in the bit rate detection circuit 10, asone example, the main part is constituted so as to have a first AND gate100, a second AND gate 102, a delay circuit 101, and an average valuedetection circuit 103, as shown in FIG. 9.

[0068] This embodiment is constituted so as to realize a method forconverting the data into a RZ signal to detect.

[0069]FIG. 10 is a waveform view in response to respective parts {circleover (1)} to {circle over (3)} of FIG. 9. For example, the input signal(NRZ signal) {circle over (1)} is converted into the RZ signal accordingto a clock (f₀) {circle over (2)} by the first AND gate 100 ({circleover (3)}), and it is further delayed by 1 cycle of f₀ by the delaycircuit 101 ({circle over (4)}), and a conjunction {circle over (5)}with {circle over (4)} is output from the second AND gate 102.

[0070] Next, in an output from the AND gate 102, an average value isoutput at an appropriate time constant by the average value detectioncircuit 103, whereby a voltage output in response to the bit rate to bedetected is possible.

[0071] Namely, in the example shown in FIG. 10, in the case where thebit rate is f=f₀/4, a larger average value output than the other ratesis obtained. In FIG. 5, an output of this average value detectioncircuit 103 is amplified by a linear amplifier 104 located at a latterpart of the bit rate detection circuit 10, and is converted into acorresponding digital signal by an A/D converter 105.

[0072] In FIG. 5, the clock selection circuit 11 is further constitutedso as to have a plurality of dividing circuits 111, 112 and a selector110. The basic frequency f₀ and first to n-th dividing signals f₁ tof_(n) are input to the selector 110. Accordingly, the selector 110selects and outputs a specified dividing signal by a digital signaloutput from the A/D converter 105.

[0073]FIG. 11 is a configurational example of an optical receiver towhich a configuration of the bit rate detection circuit 10 is applied inthe case where the configuration of the bit rate detection circuit 10 isdetected utilizing an edge of data. Accordingly, the configurationalexample of the optical receiver of FIG. 5 differs from only theconfiguration of the bit rate detection circuit 10.

[0074] This embodiment utilizes a fact that actual input waveforms havea fixed inclination at a change point of a signal. FIG. 12 is a diagramfor explaining this. In FIG. 12, data (DATA) and results reversing thedata (/DATA) are synthesized with each other. The embodiment of FIG. 11is constituted so that an OR output of the data (DATA) and resultsreversing the data (/DATA) is obtained by an OR gate 106.

[0075] In this synthetic output, an average value is detected at anappropriate time constant by the average detection circuit 103, therebydetecting a bit rate. Alternatively, the change points P of thesynthetic waveforms shown in FIG. 12 are counted, so that the bit ratecan be detected, too.

[0076] Furthermore, even in the embodiment shown in FIG. 11, ashandlings of the output on of the average value detection circuit 103are same with the embodiment of FIG. 5, the description is omitted.

[0077] As set forth hereinabove based on the drawings, according to thepresent invention, even if a signal of any bit rate is input, aregeneration of the clock signal can reliably be effected.

[0078] Therefore, it is possible to constitute a bit free network bymaking use of a transmission path or repeater of the existent bit rate,and flexibility of the system configuration is increased to a largeextent.

[0079] It will be appreciated that the above description of theembodiments is only for the understanding of the present invention andthat the scope of protection of the present invention is not limitedthereto. Furthermore, the claims and its equivalents are to be construedas lying within the scope of protection of the present invention.

What is claimed is:
 1. A clock regeneration circuit, comprising: a PLL circuit which includes a voltage control oscillator, for synchronizing an oscillation frequency signal of the voltage control oscillator with a phase of a reception signal; a clock extraction circuit which includes a band passing filter having a passing band width which concurrently extracts a basic waves component of the oscillation frequency signal of the voltage control oscillator and a harmonic component of a dividing signal of the oscillation frequency signal, for extracting a clock component of the reception signal; a frequency detector for detecting a different in frequencies between an output of the clock extraction circuit and an oscillation frequency of the voltage control oscillator; a filter for controlling the oscillation frequency of the voltage control oscillator of the PLL circuit at a detection output of the frequency detector; a bit rate detection circuit for detecting a bit rate of the reception signal; and a frequency selection circuit for outputting an oscillation frequency of the voltage control oscillator of the PLL circuit or a frequency signal obtained by dividing the oscillation frequency in response to the bit rate detected by the bit rate detection circuit, as a regeneration clock signal.
 2. The clock regeneration circuit according to claim 1 , wherein the clock extraction circuit further includes: a delay circuit for delaying the reception signal by the half cycle; and an EX-OR circuit for acquiring an exclusive OR operation of an output of the delay circuit and the reception signal, wherein the output of the EX-OR circuit is led to the band passing filter in the configuration.
 3. The clock regeneration circuit according to claim 1 , wherein the bit rate detection circuit includes: a first AND gate for taking a conjunction of the reception signal and the oscillation frequency signal of the voltage control oscillator of the PLL circuit; a delay circuit for delaying an output of the first AND gate by 1 cycle of the oscillation frequency signal of the voltage control oscillator; a second AND gate for taking a conjunction of an output of the first AND gate and an output of the delay circuit; and a circuit for acquiring an average value of the output of the AND gate.
 4. The clock regeneration circuit according to claim 1 , wherein the bit rate detection circuit includes: an AND gate for synthesizing the reception signal with a signal obtained by inverting the reception signal; and a circuit for acquiring an average value of the output of the AND gate.
 5. The clock regeneration circuit according to claim 1 , wherein the bit rate detection circuit includes: an AND gate for synthesizing the reception signal with a signal obtained by inverting the reception signal; and a circuit for counting a change point of the output of the AND gate.
 6. An optical signal receiver, comprising: a light receiving element for converting a received light signal into a reception electric signal; a PLL circuit which includes a voltage control oscillator, for synchronizing an oscillation frequency signal of the voltage control oscillator with a phase of a reception electric signal; a clock extraction circuit which includes a band passing filter having a passing band width which concurrently extracts a basic waves component of the oscillation frequency signal of the voltage control oscillator and a harmonic component of a dividing signal of the oscillation frequency signal, for extracting a clock component of the reception signal; a frequency detector for detecting a difference in frequencies between an output of the clock extraction circuit and an oscillation frequency of the voltage control oscillator; a loop filter for controlling the oscillation frequency of the voltage control oscillator of the PLL circuit by a detection output of the frequency detector; a discriminator for discriminating a level of the reception electric signal at a frequency timing of the output of the PLL circuit to output discrimination data; a bit rate detection circuit for detecting a bit rate of the reception signal; and a frequency selection circuit for outputting an oscillation frequency of the voltage control oscillator of the PLL circuit or a frequency signal obtained by dividing the oscillation frequency in response to the bit rate detected by the bit rate detection circuit, as a regeneration clock signal. 